Owns end-to-end product architecture from concept through silicon qualification, arbitrates the power/performance/area trade-offs that set competitiveness, and is the final technical authority across design, process and product engineering.
This role is the most senior technical individual contributor in memory design.
Define the memory subsystem architecture (array, periphery, I/O, redundancy, test, reliability) and turn product requirements into a design spec.
Drive floorplan and physical architecture: array efficiency, periphery partitioning, power delivery, die-level signal integrity.
Own the multi-generation roadmap: node migration, density and performance scaling.
MS/PhD in EE, CE or related field.
2+ memory products owned from architecture through production silicon.
Deep advanced CMOS FinFET expertise: layout, variability, reliability, DFM.
Memory architecture breadth (DRAM, NAND/NOR, SRAM, emerging NVM), depth in one.
Experience: Senior-level · 15+ years · Job type: Full-time
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