Design Verification Engineer

You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.

Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.

Support mixed-signal co-simulation using Verilog models of analog IP.

Develop testbench, test cases, reference model, coverage model and automation of regression suite.

Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.

Advanced knowledge of System Verilog and the UVM methodology.

Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.

Good practice of one scripting language (Perl, Python, Tcl) no preference.